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UL634H256
Low Voltage PowerStore 32K x 8 nvSRAM
Features High-performance CMOS nonvolatile static RAM 32768 x 8 bits 35 and 45 ns Access Times 15 and 20 ns Output Enable Access Times ICC = 8 mA typ. at 200 ns Cycle Time Automatic STORE to EEPROM on Power Down using external capacitor Software initiated STORE Automatic STORE Timing 106 STORE cycles to EEPROM 100 years data retention in EEPROM Automatic RECALL on Power Up Software RECALL Initiation Unlimited RECALL cycles from EEPROM Wide voltage range: 2.7 ... 3.6 V (3.0 ... 3.6 V for 35 ns type) Operating temperature range: 0 to 70 C -40 to 85 C QS 9000 Quality Standard ESD protection > 2000 V (MIL STD 883C M3015.7-HBM) RoHS compliance and Pb- free Package: SOP 32 (300 mil) Description The UL634H256 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The UL634H256 is a fast static RAM (35 and 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in an external 68 F capacitor. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on power up. The UL634H256 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. STORE cycles also may be initiated under user control via a software sequence or via a single pin (HSB). Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. RECALL cycles may also be initiated by a software sequence. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times.
Pin Configuration
Pin Description
Signal Name
VCAP A14 A12 A7 A6 A5 A4 A3 n.c. A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCCX HSB W A13 A8 A9 A11 G n.c. A10 E DQ7 DQ6 DQ5 DQ4 DQ3 G A11 A9 A8 A13 W HSB VCCX VCAP A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 n.c. A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 n.c.
Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground Capacitor Hardware Controlled Store/Busy
A0 - A14 DQ0 - DQ7 E G W VCCX VSS VCAP HSB
SOP
TSOP
Top View
Top View
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UL634H256
Block Diagram
A5 A6 A7 A8 A9 A11 A12 A13 A14 DQ0 DQ1 Input Buffers DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 EEPROM Array 512 x (64 x 8) STORE Row Decoder SRAM Array 512 Rows x 64 x 8 Columns
Store/ Recall Control
VCCX VSS VCAP
Power Control
RECALL
VCCX VCAP
HSB
Column I/O Column Decoder
Software Detect
A0 - A13
A0 A1 A2 A3 A4 A10
G
E W
Truth Table for SRAM Operations Operating Mode Standby/not selected Internal Read Read Write *H or L Characteristics
All voltages are referenced to V SS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of V I, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured 200 mV from steady-state voltage.
E H L L L
HSB H H H H
W
*
G
*
DQ0 - DQ7 High-Z High-Z Data Outputs Low-Z Data Inputs High-Z
H H L
H L
*
Absolute Maximum Ratingsa Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature C-Type K-Type A-Type
Symbol VCC VI VO PD Ta
Min. -0.5 -0.3 -0.3
Max. 4.6 VCC+0.5 VCC+0.5 1
Unit V V V W C C C C
0 -40 -40 -65
70 85 125 150
Storage Temperature
a:
Tstg
Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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UL634H256
Recommended Operating Conditions Power Supply Voltageb Symbol VCC Conditions tc = 35 ns tc = 45 ns -2 V at Pulse Width 10 ns permitted Min. 3.0 2.7 -0.3 2.2 Max. 3.6 3.6 0.8 VCC+0.3 Unit V V V V
Input Low Voltage Input High Voltage
VIL VIH
C-Type DC Characteristics Operating Supply Currentc Symbol ICC1 VCC VIL VIH tc tc Average Supply Current during STOREc ICC2 VCC E W VIL VIH VCC VIL VIH VCC E tc tc Operating Supply Current at tcR = 200 ns c (Cycling CMOS Input Levels) Standby Supply Curentd (Stable CMOS Input Levels) ICC3 VCC W VIL VIH VCC E VIL VIH Conditions Min. = 3.6 V = 0.8 V = 2.2 V = 35 ns = 45 ns = 3.6 V 0.2 V VCC-0.2 V 0.2 V VCC-0.2 V = 2.7 V = 0.2 V VCC-0.2 V = 3.6 V = VIH = 35 ns = 45 ns = 3.6 V VCC-0.2 V 0.2 V VCC-0.2 V = 3.6 V VCC-0.2 V 0.2 V VCC-0.2 V 11 9 10 45 35 3 Max.
K-Type Min. Max.
A-Type Unit Min. Max.
47 37 4
40 4
mA mA mA
Average Supply Current during PowerStore Cycle Standby Supply Currentd (Cycling TTL Input Levels)
ICC4
2
2
3
mA
ICC(SB)1
12 10 11
12 12
mA mA mA
ICC(SB)
1
1
1
mA
b: VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is connected to ground. c: ICC1 and ICC3 are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded. The current ICC1 is measured for WRITE/READ - ratio of 1/2. ICC2 is the average current required for the duration of the STORE cycle (STORE Cycle Time). d: Bringing E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
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UL634H256
DC Characteristics Symbol VCC IOH IOL VCC VOH VOL VCC High Low Output Leakage Current High at Three-State- Output Low at Three-State- Output IOHZ IOLZ IIH IIL VIH VIL VCC VOH VOL Conditions = VCCmin =-2 mA = 2 mA = VCCmin = 2.4 V = 0.4 V = 3.6 V = 3.6 V = 0V = 3.6 V = 3.6 V = 0V 1 -1 A A 1 -1 A A Min. Max. Unit
Output High Voltage Output Low Voltage Output High Current Output Low Current Input Leakage Current
VOH VOL IOH IOL
2.4 0.4 -2 2
V V mA mA
SRAM Memory Operations
No. 1 2 3 4 5 6 7 8 9
Switching Characteristics Read Cycle Read Cycle Timef Address Access Time to Data Validg Chip Enable Access Time to Data Valid Output Enable Access Time to Data Valid E HIGH to Output in High-Zh G HIGH to Output in High-Zh E LOW to Output in Low-Z G LOW to Output in Low-Z Output Hold Time after Address Change
Symbol Alt. tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX tELICCH tEHICCL IEC tcR ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) tv(A) tPU tPD 5 0 3 0 Min. 35
35 Max. Min. 45 35 35 15 13 13 5 0 3 0 35
45 Unit Max. ns 45 45 20 15 15 ns ns ns ns ns ns ns ns ns 45 ns
10 Chip Enable to Power Activee 11 Chip Disable to Power Standbyd, e
e: f: g: h:
Parameter guaranteed but not tested. Device is continuously selected with E and G both LOW. Address valid prior to or coincident with E transition LOW. Measured 200 mV from steady state output voltage.
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UL634H256
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V IL, W = VIH)f
tcR (1)
Ai DQi
Output Previous Data Valid tv(A) (9)
Address Valid ta(A) (2) Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = V IH)g
tcR (1)
Ai E G DQi
Output High Impedance
Address Valid ta(A) (2) ta(E) (3) ten(E) (7) ten(G) (8) tPU (10) ACTIVE STANDBY ta(G) (4)
tPD (11) tdis(E) (5)
tdis(G) (6) Output Data Valid
ICC
No.
Switching Characteristics Write Cycle
Symbol Alt. #1 Alt. #2 tAVAV tWLWH tWLEH tAVWL tAVWH tELWH tELEH tDVWH tWHDX tWHAX tWLQZ tWHQX tDVEH tEHDX tEHAX tAVEL tAVEH tAVAV IEC tcW tw(W) tsu(W) tsu(A) tsu(A-WH) tsu(E) tw(E) tsu(D) th(D) th(A) tdis(W) ten(W) 5
Min.
35
Max.
45 Unit Min. 45 30 30 0 30 30 30 15 0 0 13 5 15 Max. ns ns ns ns ns ns ns ns ns ns ns ns
12 Write Cycle Time 13 Write Pulse Width 14 Write Pulse Width Setup Time 15 Address Setup Time 16 Address Valid to End of Write 17 Chip Enable Setup Time 18 Chip Enable to End of Write 19 Data Setup Time to End of Write 20 Data Hold Time after End of Write 21 Address Hold after End of Write 22 W LOW to Output in High-Zh, i 23 W HIGH to Output in Low-Z
35 25 25 0 25 25 25 12 0 0
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UL634H256
Write Cycle #1: W-controlledj
tcW (12)
Ai E W
tsu(A)
Address Valid tsu(E) (17) tsu(A-WH) (16) tw(W) (13) tsu(D) (19) tdis(W) (22) Previous Data
th(A) (21)
DQi
Input
(15)
th(D) (20)
Input Data Valid ten(W) (23) High Impedance
DQi
Output
Write Cycle #2: E-controlledj
tcW (12)
Ai E W DQi
Input tsu(A)
(15)
Address Valid tw(E) (18)
th(A) (21)
tsu(W) (14) tsu(D) (19) th(D) (20)
Input Data Valid High Impedance
DQi
Output
undefined
L- to H-level
H- to L-level
i: j:
If W is LOW and when E goes LOW, the outputs remain in the high impedance state. E or W must be VIH during address transition.
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UL634H256
Nonvolatile Memory Operations Mode Selection
E H L L L
W X H L H
HSB H H H H
A13 - A0 (hex) X X X 0E38 31C7 03E0 3C1F 303F 0FC0 0E38 31C7 03E0 3C1F 303F 0C63 X
Mode Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL STORE/Inhibit
I/O Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Output High Z
Power Standby Active Active Active
Notes
l
k, l k, l k, l k, l k, l k k, l k, l k, l k, l k, l k m
L
H
H
Active
X
k:
X
L
ICC2/Standby
The six consecutive addresses must be in order listed (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a Store cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details. The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C. l: I/O state assumes that G VIL. Activation of nonvolatile cycles does not depend on the state of G. m: HSB initiated STORE operation actually occurs only if a WRITE has been done since last STORE operation. After the STORE (if any) completes, the part will go into standby mode inhibiting all operation until HSB rises.
No.
PowerStore Power Up RECALL/ Hardware Controlled STORE
Symbol Conditions Alt. tRESTORE tHLQX tHLQZ tHHQX tHLHX IHSBOL IHSBOH VSWITCH td(H)S tdis(H)S ten(H)S tw(H)S HSB = VOL HSB = VIL 20 1.8 5 2.4 60 2.7 VCC > 2.7 V 500 700 IEC 650 10 s ms ns ns ns mA A V Min. Max. Unit
24 Power Up RECALL Duration n, e 25 STORE Cycle Duration 26 HSB Low to Inhibit On e 27 HSB High to Inhibit Offe 28 External STORE Pulse Width e HSB Output Low Currente,o HSB Output High Currente, o Low Voltage Trigger Level
n: o:
tRESTORE starts from the time VCC rises above VSWITCH. HSB is an I/O that has a week internal pullup; it is basically an open drain output. It is meant to allow up to 32 UL634H256 to be ganged together for simultaneous storing. Do not use HSB to pullup any external circuitry other than other UL634H256 HSB pins.
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UL634H256
PowerStore and Automatic Power Up RECALL VCAP 3.0 V VSWITCH
t PowerStore tPDSTOREp Power Up RECALL W DQi POWER UP BROWN OUT NO STORE RECALL (NO SRAM WRITES) Hardware Controlled STORE HSB DQi
tw(H)Sq (28) tdis(H)S (26) Previous Data Valid Output td(H)S (25) ten(H)S (27) High Impedance Data Valid
(24)
(24)
tRESTORE
tRESTORE tDELAYp
BROWN OUT PowerStore
Software Controlled STORE/ No. RECALL Cycle 29 STORE/RECALL Initiation Time 30 Chip Enable to Output Inactive s 31 STORE Cycle Time 32 RECALL Cycle Timer 33 Address Setup to Chip Enable t 34 Chip Enable Pulse Width s, t 35 Chip Disable to Address Change t
Symbol Alt. tAVAV tELQZ tELQXS tELQXR tAVELN tELEHN tEHAXN IEC tcR tdis(E)SR td(E)S td(E)R tsu(A)SR tw(E)SR th(A)SR 0 25 0
Min.
35
Max.
45 Unit Min. 45 600 10 20 0 30 0 600 10 20 Max. ns ns ms s ns ns ns
35
p: tPDSTORE approximate td(E)S or td(H)S; tDELAY approximate tdis(H)S. q: After tw(H)S HSB is hold down internal by STORE operation. r: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE . VCC must not drop below VSWITCH once it has been exceeded for the RECALL to function properly. s: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs. t: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
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UL634H256
Software Controlled STORE/RECALL Cyclet, u, v, w (E = HIGH after STORE initiation)
tcR (29)
tcR (29) ADDRESS 6 th(A)SR (35) tw(E)SR tdis(E) (5) (34) (33) tsu(A)SR td(E)S (31) td(E)R
(32)
Ai E DQi
Output
ADDRESS 1
(34)
tsu(A)SR (33) High Impedance
tw(E)SR
(35) th(A)SR
VALID
VALID tdis(E)SR (30)
Software Controlled STORE/RECALL Cyclet, u, v, w (E = LOW after STORE initiation)
tcR (29)
Ai E DQi
Output tsu(A)SR (33)
ADDRESS 1 tw(E)SR
(34) (35) th(A)SR (33)
ADDRESS 6 th(A)SR td(E)S (31) VALID tdis(E)SR (30)
(35)
High Impedance
tsu(A)SR
td(E)R (32)
VALID
u: If the chip enable pulse width is less then ta(E) (see READ cycle) but greater than or equal to tw(E)SR, then the data may not be valid at the end of the low pulse, however the STORE or RECALL will still be initiated. v: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the UL634H256 performs a STORE or RECALL. w: E must be used to clock in the address sequence for the software controlled STORE and RECALL cycles
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UL634H256
Test Configuration for Functional Check
3V
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 HSB E W G
VCCX Y
VCAP
relevant test measurement
Input level according to the
VIH
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
VIL
ment of all 8 output pins
Simultaneous measure-
DQ0
1.1 k
VO 30 pF x 950
HSB
VSS
x: In measurement of tdis-times and ten-times the capacitance is 5 pF. y: Between VCC and V SS must be connected a high frequency bypass capacitor 0.1 F to avoid disturbances.
Capacitancee Input Capacitance Output Capacitance
Conditions VCC VI f Ta = 3.0 V = VSS = 1 MHz = 25 C
Symbol CI CO
Min.
Max. 8 7
Unit pF pF
All Pins not under test must be connected with ground by capacitors. Ordering Code Example Type Package S = SOP32 (300mil) UL634H256 S C 45 G1 Leadfree Option blank = Standard Package G1 = Leadfree Green Package z Access Time 35 = 35 ns (VCC = 3.0 ... 3.6 V) 45 = 45 ns (VCC = 2.7 ... 3.6 V)
Operating Temperature Range C = 0 to 70 C K = -40 to 85 C
z: on special request
Device Marking (example) Product specification
ZMD UL634H256SC 45 Z 0425 G1
Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package
Internal Code
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UL634H256
Device Operation The UL634H256 has two separate modes of operation: SRAM mode and nonvolatile mode. The memory operates in SRAM mode as a standard fast static RAM. Data is transferred in nonvolatile mode from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled. STORE cycles may be initiated under user control via a software sequence or HSB assertion and are also automatically initiated when the power supply voltage level of the chip falls below VSWITCH. RECALL operations are automatically initiated upon power up and may also occur when the VCCX rises above VSWITCH , after a low power condition. RECALL cycles may also be initiated by a software sequence. SRAM READ The UL634H256 performs a READ cycle whenever E and G are LOW and HSB and W are HIGH. The address specified on pins A0 - A14 determines which of the 32768 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tcR. If the READ is initiated by E or G, the outputs will be valid at ta(E) or at ta(G), whichever is later. The data outputs will repeatedly respond to address changes within the tcR access time without the need for transition on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W or HSB is brought LOW. SRAM WRITE Software Nonvolatile STORE A WRITE cycle is performed whenever E and W are LOW and HSB is HIGH. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes HIGH at the end of the cycle. The data on pins DQ0 - 7 will be written into the memory if it is valid tsu(D) before the end of a W controlled WRITE or tsu(D) before the end of an E controlled WRITE. It is recommended that G is kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tdis(W) after W goes LOW. Automatic STORE During normal operation, the UL634H256 will draw current from VCCX to charge up a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the VCCX pin drops below VSWITCH , the part will automatically disconnect the VCAP pin from VCCX April 7, 2005 11 The UL634H256 software controlled STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the UL634H256 implements nonvolatile operation while remaining compatible with standard 32K x 8 SRAMs. During the STORE cycle, an erase of the previous nonvolatile data is performed first, followed by a parallel programming of all nonvolatile elements. Once a STORE cycle is initiated, further inputs and outputs are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted. To initiate the STORE cycle the following READ sequence must be performed: and initiate a STORE operation. Figure 1 shows the proper connection of capacitors for automatic STORE operation. The charge storage capacitor should have a capacity of 68 F ( 20 %) at 6 V. Each UL634H256 must have its own 68 F capacitor. Each UL634H256 must have a high quality, high frequency bypass capacitor of 0.1 F connected between VCAP and VSS, using leads and traces that are short as possible. This capacitor does not replace the normal expected high frequency bypass capacitor between the power supply voltage and VSS. In order to prevent unneeded STORE operations, automatic STOREs as well as those initiated by externally driving HSB LOW will be ignored unless at least one WRITE operation has taken place since the most recent STORE cycle. Note that if HSB is driven LOW via external circuitry and no WRITES have taken place, the part will still be disabled until HSB is allowed to return HIGH. Software initiated STORE cycles are performed regardless of whether or not a WRITE operation has taken place. Automatic RECALL During power up, an automatic RECALL takes place. At a low power condition (power supply voltage < VSWITCH) an internal RECALL request may be latched. As soon as power supply voltage exceeds the sense voltage of VSWITCH, a requested RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the UL634H256 is in a WRITE state at the end of power up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10 k resistor should be connected between W and power supply voltage.
UL634H256
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 31C7 03E0 3C1F 303F 0FC0 (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE the STORE operation will begin immediately. HARDWARE-STORE-BUSY (HSB) is a high speed, low drive capability bidirectional control line. In order to allow a bank of UL634H256s to perform synchronized STORE functions, the HSB pin from a number of chips may be connected together. Each chip contains a small internal current source to pull HSB HIGH when it is not being driven LOW. To decrease the sensitivity of this signal to noise generated on the PC board, it may optionally be pulled to power supply via an external resistor with a value such that the combined load of the resistor and all parallel chip connections does not exceed IHSBOL at VOL (see Figure 1 and 2). Only if HSB is to be connected to external circuits, an external pull-up resistor should be used. During any STORE operation, regardless of how it was initiated, the UL634H256 will continue to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of a STORE operation, the part will be disabled until HSB actually goes HIGH. Hardware Protection The UL634H256 offers hardware protection against inadvertent STORE operation during low voltage conditions. When VCAP < VSWITCH, all software or HSB initiated STORE operations will be inhibited. Preventing Automatic STORES The PowerStore function can be disabled on the fly by holding HSB HIGH with a driver capable of sourcing 15 mA at V OH of at least 2.2 V as it will have to overpower the internal pull-down device that drives HSB LOW for 50 ns at the onset of a PowerStore. When the UL634H256 is connected for PowerStore operation (see Figure 1) and VCCX crosses VSWITCH on the way down, the UL634H256 will attempt to pull HSB LOW; if HSB doesnt actually get below VIL, the part will stop trying to pull HSB LOW and abort the PowerStore attempt. Disabling Automatic STORES If the PowerStore function is not required, then V CAP should be tied directly to the power supply and VCCX should by tied to ground. In this mode, STORE operation may be triggered through software control or the HSB pin. In either event, VCAP (Pin 1) must always have a proper bypass capacitor connected to it (Figure 2).
Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles are used in the sequence, although it is not necessary that G is LOW for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. Software Nonvolatile RECALL A RECALL cycle of the EEPROM data into the SRAM is initiated with a sequence of READ operations in a manner similar to the STORE initiation. To initiate the RECALL cycle the following sequence of READ operations must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 31C7 03E0 3C1F 303F 0C63 (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL
Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. HSB Nonvolatile STORE The hardware controlled STORE Busy pin (HSB) is connected to an open drain circuit acting as both input and output to perform two different functions. When driven LOW by the internal chip circuitry it indicates that a STORE operation (initiated via any means) is in progress within the chip. When driven LOW by external circuitry for longer than tw(H)S, the chip will conditionally initiate a STORE operation after tdis(H)S. READ and WRITE operations that are in progress when HSB is driven LOW (either by internal or external circuitry) will be allowed to complete before the STORE operation is performed, in the following manner. After HSB goes LOW, the part will continue normal SRAM operation for tdis(H)S. During tdis(H)S, a transition on any address or control signal will terminate SRAM operation and cause the STORE to commence. Note that if an SRAM WRITE is attempted after HSB has been forced LOW, the WRITE will not occur and
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UL634H256
Disabling Automatic STORES: STORE Cycle Inhibit and Automatic Power Up RECALL VCAP 3.0 V VSWITCH
t STORE inhibit Power Up RECALL
(24)
tRESTORE
Power Supply VCAP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCCX HSB Power Supply 10 k (optional, see description HSB nonvolatile store) 0.1 F Bypass VCAP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCCX HSB 10 k (optional, see description HSB nonvolatile store)
+
68 F 20 % 0.1 F Bypass
VSS
VSS
Figure 1: Automatic STORE Operation Schematic Diagram
Figure 2: Disabling Automatic STORES Schematic Diagram
Low Average Active Power The UL634H256 has been designed to draw significantly less power when E is LOW (chip enabled) but the access cycle time is longer than 45 ns. When E is HIGH the chip consumes only standby current. The overall average current drawn by the part depends on the following items: 1. CMOS or TTL input levels 2. the time during which the chip is disabled (E HIGH) 3. the cycle time for accesses (E LOW) 4. the ratio of READs to WRITEs 5. the operating temperature 6. the power supply voltage level
The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.
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UL634H256
LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMD's warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice.
April 7, 2005
Zentrum Mikroelektronik Dresden AG Grenzstrae 28 * D-01109 Dresden * P. O. B. 80 01 34 * D-01101 Dresden * Germany Phone: +49 351 8822 306 * Fax: +49 351 8822 337 * Email: memory@zmd.de * http://www.zmd.de

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